The fabrication of various solid state devices requires the use of planar substrates, or semiconductor wafers, on which integrated circuits are fabricated. The final number, or yield, of functional integrated circuits on a wafer at the end of the IC fabrication process is of utmost importance to semiconductor manufacturers, and increasing the yield of circuits on the wafer is the main goal of semiconductor fabrication. After packaging, the circuits on the wafers are tested, wherein non-functional dies are marked using an inking process and the functional dies on the wafer are separated and sold. IC fabricators increase the yield of dies on a wafer by exploiting economies of scale. Over 1000 dies may be formed on a single wafer which measures from six to twelve inches in diameter.
Various processing steps are used to fabricate integrated circuits on a semiconductor wafer. These steps include sequential deposition of conductive and insulative layers on the silicon wafer substrate; formation of a photoresist or other mask such as titanium oxide or silicon oxide, in the form of the desired metal interconnection pattern, using standard lithographic or photolithographic techniques; subjecting the wafer substrate to a dry etching process to remove material from one or more conducting layers from the areas not covered by the mask, thereby etching the conducting layer or layers in the form of the masked pattern on the substrate; removing or stripping the mask layer from the substrate typically using reactive plasma and chlorine gas, thereby exposing the top surface of the conductive interconnect layer; and cooling and drying the wafer substrate by applying water and nitrogen gas to the wafer substrate.
The numerous processing steps outlined above are used to cumulatively apply multiple electrically conductive and insulative layers on the wafer and pattern the layers to form the circuits. The final yield of functional circuits on the wafer depends on proper application of each layer during the process steps. Proper application of those layers depends, in turn, on coating the material in a uniform spread over the surface of the wafer in an economical and efficient manner.
Plasma vapor deposition (PVD) is frequently used to deposit metal conductive layers for interconnect metallization on a substrate. Any chemical residue or oxide which remains on the substrate prior to the PVD process can act as a dielectric shield and prevent the subsequently-deposited PVD film from uniformly adhering to the substrate. Therefore, prior to the PVD process, each substrate frequently undergoes a pre-cleaning process in a pre-clean chamber to remove chemical residues or oxides which may be formed while the substrate is exposed to the clean room atmosphere. The pre-cleaning process is carried out in a pre-clean chamber, which applies a light, non-selective, non-reactive plasma etch to the substrate to remove chemical residues such as oxides remaining on the substrate surface.
Referring to the schematic of FIG. 1, a typical conventional pre-clean chamber is generally indicated by reference numeral 10 and typically includes a chamber base 12 having a typically grounded chamber wall 14. The chamber base 12 is closed by a removable lid or cover 22 and contains a pedestal assembly 18 which can typically be raised and lowered on a shaft 20 by actuation of a pedestal lift assembly 16. An ICP (inductively-coupled plasma) coil 24 surrounds the upper portion of the pre-clean chamber 10 and is connected to an RF source power supply 26 which operates at a frequency of typically about 400 KHz. The pedestal assembly 18 is connected, through an RF match network 30 which matches impedences, to an RF bias power supply 28 which operates at a frequency of typically about 13.56 MHz.
During operation of the pre-clean chamber 10, the pedestal assembly 18 supports a wafer substrate 32 in the chamber base 12. A plasma-generating source gas, such as argon, is introduced into the chamber 10 by a gas supply (not shown). Volatile reaction products and unreacted plasma species are removed from the chamber 10 by a gas removal mechanism (not shown).
Source power such as a high voltage signal, provided by the RF source power supply 26, is applied to the ICP coil 24 to ignite and sustain a plasma in the chamber 10. Ignition of a plasma in the chamber 10 is accomplished primarily by electrostatic coupling of the ICP coil 24 with the source gas, due to the large-magnitude voltage applied to the ICP coil 24 and the resulting electric fields produced in the chamber 10. Once ignited, the plasma is sustained by electromagnetic induction effects associated with time-varying magnetic fields produced by the alternating currents applied to the ICP coil 24. Through the RF bias power supply 28, the pedestal assembly 18 is typically electrically biased to provide to the substrate 32 ion energies that are independent of the RF voltage applied to the chamber 10 through the ICP coil 24 and RF source power supply 26. This facilitates more precise control over the energies of the etchant ions that bombard the surface of the substrate 32.
As shown in FIG. 2, the pedestal assembly 18 typically includes a pedestal 34 which is aluminum, titanium or other non-reactive metal. The pedestal 34 is seated in an insulator 36, which is typically a non-reactive insulative material such as ceramic or quartz. Multiple lift pin openings 38 may extend through the pedestal assembly 18 and receive respective lift pins (not shown) for the lowering and lifting of a substrate 32 onto and from, respectively, a quartz cover plate 40 provided on the pedestal 34. Multiple (typically three) antennae 42, each of which is typically polysilicon, extend through respective openings provided in the insulator 36 and contact the pedestal 34. The antennae 42 apply bias power from the bias power supply 28 to the substrate 32. During the pre-clean process, the insulator 36 inhibits conductivity to the pedestal 34 and other parts of the pedestal assembly 18, thereby confining the etchant plasma to the surface of the substrate 32.
One of the problems associated with the conventional pre-clean chamber 10 is that the multiple antennae 42 are exposed to the interior of the chamber 10 through respective slots or windows (not shown) provided in the insulator 36. While this facilitates accurate and stable measurements of the bias power applied to the pedestal 34 through the bias power supply 28, in the event that the antennae 42 are installed incorrectly in the insulator 36, an impedence mismatch may occur. As a result, plasma may produce a high reflective power in the chamber 10 and damage the antennae 42. The damaged antennae 42 serve as a major source of particles which may potentially contaminate devices being fabricated on the substrate 32.
Moreover, because each of the antennae 42 is typically held in place using a copper clip (not shown) which conducts electrical current between the pedestal 34 and the antenna 42, the antennae 42 may serve as conduits for electrical arcing between the pedestal 34 and the chamber wall 14. Such electrical arcing induces operational power loss and requires re-tuning of the source power supply 26 and/or the RF match network 30 to stabilize the operational power. Therefore, a process is needed for reducing the generation of potential device-contaminating particles and preventing electrical arcing in a pre-clean chamber during a substrate pre-clean process.
An object of the present invention is to provide a novel process which is suitable for reducing the generation of particles during a pre-clean or other etch process.
Another object of the present invention is to provide a novel process which is suitable for preventing electrical arcing in a pre-clean or other etch chamber.
Still another object of the present invention is to provide a novel process which is suitable for preventing contamination of devices being fabricated on a substrate.
Yet another object of the present invention is to provide a novel process which increases the yield of devices fabricated on a substrate.
A still further object of the present invention is to provide a novel process for reducing formation of particles in an antenna-containing pre-clean or other etch chamber, which process includes removing the particle-generating antennae from the chamber.
Yet another object of the present invention is to provide a novel process for reducing the generation of particles in a pre-clean or etch chamber, which process includes the removal of potential particle-generating antennae from the chamber and may further include a multi-step plasma ignition control or power adjustment sequence to match chamber impedences and reduce reflective power and enhance process stability in a pre-clean or etch process.